JTAG Debug Interface
The JTAG Interface provides a standard test interface to an embedded system.
The JTAG Interface provides a full debug and production test and programming interface.
It has two components, one implements the TAP controller and boundary scan architecture the other provides specific system level test and debug features.
The DMA interface ensures that, via the JTAG interface, external debuggers have full access to the system.
The JTAG Interface has the following features:
- Standard 4 pin connection: tms, tdi, tdo, and tck
- IEEE 1149.1
- Fully supported in the GDB debugger for APS processors
- Can be chained with other JTAG interfaces
- Full bus master DMA interface
- Can wake up the CPU