Processor IP

Cortus Advanced Processing Solutions (APS) and Floating Point Solutions (FPS) are all 32- bit RISC processor IP designed to efficiently execute instructions in higher level languages.  Cortus processors feature the same instruction set architecture but differ in performance, power, and area. The APS family of processors are ideal for applications requiring performance/power efficiency with minimal area. Applications demanding more performance and floating point operations will find the  FPS processors ideal. A selection of our processor IP is shown here other processors are available and under development, please contact us if you have a more specialised requirement.

All Cortus processors feature:
  • Optimisations for executing C/C++
  • Latency hiding out–of–order completion
  • Eclipse and GNU based C/C++ toolchain and IDE
  • SystemC models and Instruction Set Simulators

8 bit replacement, simple control and FSM

APS1 Datasheet

General purpose, low power, small silicon footprint

APS3R Datasheet

High performance, sophisticated control

APS25 Datasheet

Numerical applications, high performance, floating point

FPS26 Datasheet

Very high performance, high throughput & signal processing. Dual issue pipeline.

APS29 Datasheet

If you’re looking to move up to a 32 bit processor from an 8 bit microcontroller, look no further than the APS1. A fully 32 bit implementation, the APS1 was designed to provide the smallest available silicon area, excellent code density, and minimum power consumption while providing a significant performance improvement over 8 bit microcontrollers.

The APS1 processor has the following features:

  • Sixteen 32 bit registers
  • 64 KBytes of addressable data memory
  • 64 KBytes of addressable program memory
  • 64 KBytes of peripheral address space
  • 27 external interrupts
  • SW development tools are provided:
    • Eclipse-based IDE
    • GNU GCC and all utilities ported
    • GNU GDB Debugger
    • Debug via JTAG port

The APS1 is delivered as a GTECH netlist allowing easy integration into your ASIC design and optimization for performance, power, and area. Typical results of implementing the APS1 in a UMC 90nm CMOS process are:

  • Gate count: from  7,700
  • Silicon area: 0.039 mm²
  • Power consumption: 9.5 μW/MHz
  • Frequency Maximum: 300 MHz

The APS3R is the workhorse of the Cortus processor family designed specifically to meet the needs of embedded systems. Ideal for applications requiring energy efficiency yet high performance such as wireless communications, sensing, SIM cards, networking, and security applications.

The APS3R is an enhanced version of the APS3, providing improved performance for a fractional increase in silicon area. All instructions are 16 bits in length, with a 16 bit extension when needed (no mode switches necessary) providing excellent code density. The pipeline features out-of-order execution enabling nearly all instructions to execute in a single cycle, including loads and stores. Interrupts are fully vectored and the architecture ensures a minimum of software overhead in task switches. The processor was designed to execute high level languages with excellent efficiency.

The APS3R has the following features:

  • Sixteen 32 bit registers
  • 4 GByte address space
  • 251 external interrupts
  • SW development tools are provided:
    • Eclipse-based IDE
    • GNU GCC and all utilities ported
    • GNU GDB Debugger
    • Debug via JTAG port

The APS3R is delivered as RTL code with synthesis scripts and constraints allowing easy integration into your ASIC design and optimization for performance, power, and area. Typical results of implementing the APS3R in a UMC 90nm CMOS process are:

  • Gate count: from 8,700
  • Silicon area: 0.049 mm²
  • Power consumption: 11.61 μW/MHz
  • Frequency Maximum: 300 MHz

The APS25 is a fully 32 bit high performance general purpose CPU capable of meeting the demands of most computing tasks.  It is suitable for creating complex embedded systems with caches,
co-processors and multiple cores. Designed for advanced control and communication applications, it is well suited for complex sensors, embedded vision, security (encryption, decryption), home automation, and military and aerospace applications.

The APS25 is an enhanced version of the APS5 that utilizes the 2nd generation Cortus Instruction Set Architecture to provide improved code density with only a marginal increase in silicon area. The instructions are 16, 24 and 32 bits in length ensuring optimal code density. The 5-7 stage pipeline ensures ultra low power consumption and high performance while retaining a reasonable maximum clock frequency. Out-of-order completion enables nearly all instructions to execute in a single cycle, including loads and stores. Interrupts are fully vectored and the architecture ensures a minimum of software overhead in task switches.

The APS25 has the following features:

  • Sixteen 32 bit general purpose registers
  • Harvard architecture with 2 × 4 GByte address space
  • 251 external interrupts
  • High computation performance
    • Integer Multiply & Divide
    • Dual & Multi-Core Capable
    • Co-Processor Interface
    • AXI4 buses
    • Optional Caches
  • SW development tools are provided:
    • Eclipse-based IDE
    • GNU GCC and all utilities ported
    • GNU GDB Debugger
    • Debug via JTAG port

The APS25 is delivered as RTL code with synthesis scripts and constraints allowing easy integration into your ASIC design and optimization for performance, power, and area. Typical results of implementing the APS25 in a UMC 90nm CMOS process are:

    • Gate count: from 18,800
    • Silicon area: 0.099 mm²
    • Power consumption: 19.3 μW/MHz
    • Frequency Maximum: 344 MHz

The FPS26 is a high performance, extendible 32 bit microcontroller core featuring a single precision floating point combined with excellent code density. It is suitable for creating complex embedded systems with caches, co-processors and multiple cores.

Designed for advanced control and communication applications, it is well suited to complex sensors, sophisticated home automation, audio, vision, and wireless applications.

Floating point arithmetic benefits a number of algorithms. One example is matrix inversion, which is a key operation required for Multiple Input / Multiple Output (MIMO) technologies that are becoming widespread in wireless communications. Another example is Fast Fourier Transforms (FFTs) which often suffer from scaling problems in fixed point. Algorithms for machine vision and medical imaging also benefit from the dynamic range offered.

The FPS26 has the following features:

  • IEEE 754 Single Precision Arithmetic
  • Sixteen 32 bit general purpose registers
  • Harvard architecture with 2 × 4 GByte address space
  • 251 external interrupts
  • High computation performance
    • Integer Multiply & Divide
    • Dual & Multi-Core Capable
    • Co-Processor Interface
    • AXI4 buses
    • Optional Caches
  • SW development tools are provided:
    • Eclipse-based IDE
    • GNU GCC and all utilities ported
    • GNU GDB Debugger
    • Debug via JTAG port

The FPS26 is delivered as RTL code with synthesis scripts and constraints allowing easy integration into your ASIC design and optimization for performance, power, and area. Typical results of implementing the FPS26 in a UMC 90nm CMOS process are:

  • Gate count: from 35,000
  • Silicon area: 0.192 mm²
  • Power consumption: 37.1 μW/MHz
  • Frequency Maximum: 392 MHz

The APS29 is a very high performance, extendible 32 bit microcontroller core featuring a dual issue pipeline and multiply-accumulate combined with excellent code density. It is suitable for creating high performance embedded systems with caches, co-processors and multiple cores.

Designed for high speed control and signal processing, it is well suited to complex sensors, audio, video and wireless applications.

The dual issue pipeline provides instruction level parallelism and increases performance yet is transparent to the programmer. There is no need to change coding styles or complex compilation schemes. All the performance increases are managed within the processor core and do not require any specific techniques from the programmer.

The dual functional units contain a single cycle ALU and multiplier/divider each, and there is one multiply-accumulate unit with a 64 bit accumulator.

A static branch predictor dramatically improves the performance of loops. All these features offer significant performance boosts but require no special programming techniques.

The APS29 has the following features:

  • Sixteen 32 bit general purpose registers
  • One 64 bit accumulator
  • Harvard architecture with 2 × 4 GByte address space
  • 251 external interrupts
  • High computation performance
    • Dual Issue Pipeline
    • Multiply – Accumulate
    • 2 High Performance Integer Multipliers
    • 2 Integer Dividers
    • Static Branch Prediction
    • Co-Processor Interface
    • AXI4 buses with 64 bit data width
    • Optional Caches
  • SW development tools are provided:
    • Eclipse-based IDE
    • GNU GCC and all utilities ported
    • GNU GDB Debugger
    • Debug via JTAG port

The APS29 is delivered as RTL code with synthesis scripts and constraints allowing easy integration into your ASIC design and optimization for performance, power, and area. Typical results of implementing the APS29 in a TSMC 28nm CMOS process are:

    • Gate count: from 45,500
    • Silicon area: 0.037 mm²
    • Power consumption: 17.54 μW/MHz
    • Maximum Frequency: 1400 MHz
APS3V

A Compact Implementation of the RISC-V RV32IMC ISA
The APS3V is our first RISC-V processor core. It offers the RV32IMC ISA, with a Harvard architecture and AXI4 lite bus interfaces.
It has a 5-7 stage pipeline and requires about 8642 gates + register file. It supports both Machine and User modes.

APS3V Datasheet

Other RISC-V processor cores are under development.

Other members of the Cortus APS family of processors are available. You may find that these more specialised implementations of the APS architecture better suit your application. Alternatively should have a more specialised requirement please contact us.

The APS5 offers approximately the same level of performance as the APS25 with a smaller core silicon footprint. It has the same code density as the APS3R. This processor core is advantageous when the projected code size is not expected to exceed about 64 Kbytes.

APS5 Datasheet

The FPS6 offers approximately the same level of performance as the FPS26 with a marginally smaller core silicon footprint. It has the same code density as the APS3R. This processor core is advantageous when the projected code size is not expected to exceed about 64 Kbytes.

FPS6 Datasheet

The APS23 offers approximately the same level of performance as the APS3R for a larger core silicon footprint. It has the same code density advantages as the APS25. This processor core should be considered if the projected code size is expected to exceed 64 Kbytes and code memory space is at a premium (typically on chip flash memory).

APS23 Datasheet