APS3S – Superior Code Density
The APS3S is a fully 32 bit general purpose CPU designed specifically to meet the needs of embedded systems.
It has improved code density compared to the APS3.
The APS3S is a modern RISC processor with Harvard architecture.
The instructions are 16 bits in length, with a 16 bit extension when needed (no mode switches necessary) plus various architectural features ensure leading code density.
The pipeline features out-of-order execution enabling nearly all instructions to execute in a single cycle, including loads and stores.
Interrupts are fully vectored and the architecture ensures a minimum of software overhead in task switches.
The processor was designed to execute high level languages, notably C, with ease.
The software application can be entirely realised in C, interrupt routines included.
The entire GNU GCC toolsuite has been ported to this architecture and is available free of charge.
The APS3S has the following features:
- Little endian
- Leading code density
- All necessary tools are available:
- GNU GCC and all utilities ported
- GNU GDB Debugger available
- Debug via JTAG
- All tools available free of charge
- 4 GByte address space
- Sixteen 32 bit general purpose registers
- Optional unaligned data access:
- makes supporting legacy 8051 code easy!
- Power efficient
- Most instructions are single cycle, including load and store
- A wide range of standard peripherals available
An optional trace buffer is available to make debugging even more rapid and easy. It is fully configurable and captures the key aspects of program execution. It is supported by the tools and can be controlled either via the JTAG interface or by the target CPU.