The APS3R is a fully 32 bit general purpose CPU designed specifically to meet the needs of embedded systems.
The APS3R is an enhanced version of the APS3, with improved performace for a fractional increase in silicon area. The instructions are 16 bits in length, with a 16 bit extension when needed (no mode switches necessary) giving excellent code density. The pipeline features out-of-order execution enabling nearly all instructions to execute in a single cycle, including loads and stores. Interrupts are fully vectored and the architecture ensures a minimum of software overhead in task switches. The processor was designed to execute high level languages, notably C, with ease. The software application can be entirely realised in C, interrupt routines included. The entire GNU GCC toolsuite has been ported to this architecture and is available free of charge.
The APS3R has the following features:
- All necessary tools are available:
- GNU GCC and all utilities ported
- GNU GDB Debugger available
- Debug via JTAG
- All tools available free of charge
- Excellent code density
- 4 GByte address space
- Sixteen 32 bit general purpose registers
- Optional unaligned data access:
- makes supporting legacy 8051 code easy!
- No bigger than an 8 bit microcontroller
- Very power efficient
- Most instructions are single cycle, including load and store
- A wide range of standard peripherals available
An optional trace buffer is available to make debugging even more rapid and easy. It is fully configurable and captures the key aspects of program execution. It is supported by the tools and can be controlled either via the JTAG interface or by the target CPU.
More details can be found in the datasheet.
The licensing of APS3R is also offered through MOSIS in conjunction with their silicon fabrication service; more details can be found in this document.